This invention describes the architecture of a multi-port memory, and more particularly, it describes a method and configuration to reduce the noise on read bitlines created during a simultaneous read and write operation in a multi-port memory.
Single port memories allow either one read or one write operation during each cycle. Typically, a single port memory consists of either six transistor static memory cells (6T SRAM) or single transistor dynamic cells (1T).
FIG. 1A shows a transistor level schematic of a typical 6T SRAM cell 0. It consists of four NMOS transistors 1, 2, 5, and 6, and two PMOS transistors 3 and 4. PMOS 3 and 4 and NMOS 5 and 6 transistors configure a CMOS cross-coupled latch, which maintains a data bit as a storage element. NMOS 1 and 2 couple nodes 7 and 8 to biltlines BL and bBL when a wordline WL is activated. This allows the data bit to be read to or written from bitlines BL and bBL.
FIG. 1B depicts a transistor level schematic of a dynamic memory cell 10. It consists of one NMOS transistor 11 and one capacitor 12 (1T DRAM cell). When the wordline WL is activated, NMOS 11 couples capacitor 12 to the bitline BL. This allows a data bit stored in capacitor 12 to be read to or written from bitline BL. Regardless whether a 6T SRAM or a 1T SRAM are used, only one WL per array can be activated at a time to perform a read or a write. Activating more than one WL creates a conflict on the common BL.
In order to improve the array utilization as well as the overall data bandwidth, a dual port memory cell and array are used to allow simultaneous access to cells on two wordlines of the same array. A subset of the true dual port memory is one that allows concurrent read and writes to cells on two different wordlines of the same array.
FIG. 2A shows a transistor level schematic for a conventional dual port static memory cell. It consists of four NMOS transistors 1A,1B,5, and 6, and two PMOS transistors 3 and 4. Unlike the 1-port SRAM cell, the gates of the NMOS switching transistors 1A and 1B couple different wordlines WL0 and WL1. By activating both WL0 and WL1, the memory cell coupling WL0 and the memory cell coupling WL1 can be simultaneously read or written through BL0 and BL1 without creating data contention.
FIG. 2B illustrates a transistor level schematic of a prior art dual port dynamic memory cell. It consists of two NMOS switching transistors 14A and 14B, and one capacitor 16. Similar to the dual port static memory cell, the gates of NMOS switching transistors 14A and 14B are coupled to different wordlines WL0 and WL1. By activating the two wordlines WL0 and WL1, the memory cell coupled to WL0 and the memory cell linked to WL1 can be simultaneously read or written through BL0 and BL1 without causing data contention.
FIG. 3A shows a transistor level schematic of a conventional 3T gain cell. The cell is provided with two independent ports. However, in contrast with the dual port cells depicted in FIG. 2, the 3T gain cell is provided with one read port and one write port. When write wordline WWL switches to high, NMOS transistor 34 couples storage node 32 to write bitline WBL when a write operation is performed. The storage node 32 is provided with a capacitor 32 to reduce the impact of leakage on the stored data bit. The data bit stored in storage node 32 can be read out to read bitline RBL when a read wordline RWL switches to high. If storage node 32 stands at high, the two NMOS transistors 31 and 33 remain on, discharging read bitline RBL. If the storage node stands at low, the NMOS transistor 33 is cut-off, keeping RBL at the precharged voltage.
FIG. 3B shows a transistor level schematic for a prior art 2T gain cell. Similar to the 3T gain cell, when write wordline WWL switches to high during a write operation, the NMOS transistor 34 will couple storage node 32 to write bitline WBL. Storage node 32 is preferably provided with a capacitor 32 to store the data bit. Unlike the 3T gain cell, the read NMOS switching transistor 31 is eliminated. The source of the NMOS transistor 32 is coupled to read wordline RWL, making it possible to perform a data bit read operation by measuring the NMOS 33 transistor resistance.
In a conventional method, a voltage between RBL and RWL is applied to read the cell. In the unselected state, both RBL and RWL are maintained at high. To read the data bits, RWL switches to low. If the stored data bit is at low, NMOS 33 remains in the off state, maintaining RBL at high. If the stored data bit stands at high, NMOS 33 remains on, forcing RBL switch to low. Both of the 3T gain cell or the 2T gain cell discussed above allow for simultaneous read and write operations.
FIG. 4 shows memory array for the 3T gain cell that allows simultaneous read and write operations. Memory 40 consists of a plurality of 3T gain cells 42 arranged in a matrix formation. While FIG. 4 shows a 3T gain cell, any cell having two general purpose ports or one read and one write port may be used. The memory cells are controlled by their corresponding read wordline RWL, write wordline WWL, read bitline RBL and write bitline WBL. The data bit on RBL is sensed by a corresponding sense amplifier 43. WBL is driven by write driver circuit 44. The memory cells 42A and 42C are placed in the write mode by activating WWL0, while memory cells 42B and 42D are placed in the read mode by activating RWL1, thereby disabling WWL1 and RWL0. The memory cell data bits in cells 42B and 42D are read out to RBL0 and RBL1, and sensed by the corresponding sense amplifiers 43. A typical differential sense amplifier utilizes a reference voltage VREF that allows discriminating between the voltage on RBL corresponding to the case of reading either a 1 or a 0 from the memory cell. The memory cell data bits in the memory cells 42A and 42C are written through WBL0 and WBL1. These bitlines, i.e., WBL0 and WBL1, are driven by the corresponding write bitline drivers 44. Often, RBL and WBL are placed in close proximity in an integrated circuit. When WBL changes voltage, the coupling capacitance between WBL and the nearby RBL causes a voltage disturbance on RBL. This noise on RBL makes it difficult or impossible to accurately sense the data bit that is being read.
FIG. 5 shows a simplified coupling noise model and simulated waveform for RBL and WBL. The analysis assumes that the data bit on RBL1 is sensed by utilizing sense amplifier 43, while the adjacent WBL0 and WBL1 are driven by write drivers 44 during a write operation. It also assumes that the read bitline RBL1 is precharged to power supply voltage VDD through PMOS 55. Assuming that the gain cell stores a low data bit, then, RBL will remain at voltage VDD. However, when the WBLs switch to high or to low, RBL switches to high or low depending on WBL voltage swing due to the coupling capacitor between RBL and WBLs. As shown by way of simulation, the coupling noise may be as large as 250 mV when the WRL swing is 1.2V, even when the PMOS load device is not disabled during the sensing operation. The coupling noise renders simultaneous read and write operations difficult or potentially impossible. In order to circumvent this problem, one may insert additional wires between each WBL and RBL held at virtual ground, effectively shielding the WBL noise. Shielding techniques eliminate the coupling noise, however, at the expense of a significantly increased cell area. The coupling noise between WBL and RBL presents a unique problem that occurs during a simultaneous read and write operation. Conventional BL twisting methods are not applicable to cancel the noise because of the single ended RBL and WBL configuration defining the dual-port cells.